The open-source RISC-V processor architecture is getting a trace function through an IP (intellectual property) block from Cambridge-based UltraSoC.
It supports both 32 and 64-bit RISC-V designs, and is intended to integrate with the firms other RISC-V offerings. “The addition of trace capabilities means that UltraSoC provides the most comprehensive RISC-V commercial debug solution,” claimed the firm.
RISC-V processor vendors Andes, Codasip, Microsemi, Roa Logic, SiFive and Syntacore are backing the trace IP, according to UltraSoC.
Processor trace is a function that allows the behaviour of a program to be viewed in instruction-by-instruction.
“On the technical level, full availability of processor trace is a key part of that development ecosystem,” said RISC-V Founation director Rick O’Connor. “Within the RISC-V Foundation, we’re working to standardise the interfaces to RISC-V cores that provide processor trace. We’re delighted to see UltraSoC supporting that effort, while also delivering commercially.”
As well as a stand-alone IP module for integration with its own SoC architecture, UltraSoC’s offers a variety of packaged options to get RISC-V designers up-and-running, ranging from a lightweight package combining simple run-control with USB as the debug interface, to solutions with both run control and trace, and interfacing via either JTAG or UltraSoC’s proprietary non-intrusive, bare-metal USB.
The firm’s embedded analytics IP will be available through the SiFive DesignShare ecosystem, and it has been selected for use in Microsemi’s RISC-V range.
UltraSoC will be at Embedded Word 2018 (Nürnburg, 27 Feb – 1 Mar) on the RISC-V stand 3A-419. Papers on RISC-V will be presented at the associated Embedded World conference.
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